1. Field of the Invention
This invention relates generally to wafer scale integration type of semiconductor circuitry and more particularly to means for defining which working sites on a processed wafer of a wafer scale integration type semiconductor structure are to be used.
2. Description of the Prior Art
Wafer scale integration (WSI) technology is an effort to achieve higher density by fabricating complete signal and data processors, for example, on a single large monolithic wafer of silicon or gallium arsenide which formerly would occupy several circuit cards. The wafer consists of a number of identical sites comprised of many discrete devices which are to be connected together to form a desired circuit function. Some WSI wafers are comprised of more than one type of site.
Inherent in any processed WSI wafer are the existence of non-working or defective sites which occur before, during or after manufacture, including testing and burn-in. As a result, a certain amount of site redundancy is built into the wafer by providing for a predetermined number of primary sites and a number of extra or spare sites. The number of primary sites is the exact number needed for a required function while the spares are provided to allow for defects. The acceptable yield is thus dependent upon some repair or defect avoidance technique employed to by-pass faulty sites and make suitable connections to functional sites. Notwithstanding that a given repair strategy is used to provide very high yields, the existence of faults, i.e. defective sites, may still be undetectable at repair time or may be introduced after repair time.
A variety of approaches have been resorted to in the past for providing for defect avoidance at some point in the fabrication process. The so-called discretionary wiring technique resorted to by some fabricators failed largely because of flaws introduced during the formation of the discretionary masks and subsequent processing. One approach to avoid a great deal of post processing repair was by making laser repairs after the circuit had been mounted in a package. This approach went far in minimizing the problem, but even there retesting had to be performed over and over again to guard against loss. Conventional practice now employed is to achieve defect avoidance using discretionary elements within the monolithic device itself. Examples of such elements include links of material which can be cut by laser, materials which can be welded together by laser, materials which can be deposited in a discretionary manner, or electronically controlled switches. They all share the same, and in some cases undesirable, characteristic of being an integral part of the monolithic structure.
Thus all strategies for the fabrication of wafer scale integrated type of semiconductor devices recognize that defective sites will exist on wafers and that some means must be provided for achieving an operational circuit in the presence of those defects. The operations performed for the purpose of defect management or defect avoidance can appear in the wafer processing sequence at any time after circuit function can be observed. The nearer this defect management or defect avoidance step occurs to the final fabrication step the better because any processing performed thereafter can introduce fatal defects. Accordingly, the logical choice would be to delay defect management and avoidance until after all processing and assembly operations have been completed.